The present invention relates to an architectural simulator and more specifically, to a method for decoding an instruction in an architectural simulator.
Generally, processes for developing a new integrated circuit or chip include hardware design, optimization and manufacturing steps. Chip simulation is used throughout all steps the process to verify chip operations at each stage and to evaluate a benchmark for optimizing chip conditions at each stage. Simulation parameters used for chip simulation are also eventually used to generate an application program for testing the chip following manufacture. Hardware Description Language (HDL) is a common low-level computer-based language for controlling such a simulation.
Generally, it takes long time to decode an instruction in a simulator environment. Therefore, if it is possible to reduce the time necessary for decoding an instruction, the total simulation time can be reduced.